In recent several years, ASIC (application specific integrated circuit) technology has evolved from a chip-set philosophy to an embedded core based system-on-a-chip (SoC) concept. An SoC IC includes various reusable blocks or cores, such as microcontrollers, interfaces, memory arrays, and DSPs (digital signal processors). Such functional blocks are commonly called "cores". FIG. 1 is a schematic diagram showing an example of inner structure of such an SoC IC. In the example of FIG. 1, an SoC 10 includes a microprocessor core 11, a memory core 13 and function specific cores 15-17, a PLL core 18, and a test access port (TAP) 19.
Large embedded (on-chip) memories are the key components in SoC ICs. These embedded memories implement register files, FIFOs (first-in-first-out), data-cache, instruction-cache, transmit/receive buffers, storage for texture processing, etc. This invention is directed to a method for testing such embedded (on-chip) memories in an SoC IC. Testing of embedded memories is generally done by one of the following methods:
(1) Direct application of test patterns to an embedded memory under test by an IC tester while accessing the memory through an I/O multiplexing: This method requires modification in the I/Os (input/output) of an SoC by adding a multiplexer therein. Due to this extra multiplexer, there is a permanent penalty, for example, a signal propagation delay, in the performance of the SoC IC. The test patterns are generated by an IC tester's pattern generator such as an ALPG (algorithmic pattern generation) unit. However, due to the multiplexer at the I/Os, the actual test patterns require serialization (parallel to serial conversion) of the ALPG patterns, which increases test complexity, test time and many time losses of at-speed testing.
(2) Test application to an embedded memory under test through local boundary scan or a collar register: This method adds a wrapper (boundary scan or shift-register type wrapper) to an embedded memory to be tested. Thus, the data transfer rate to and from the memory under test slows down by the time equal to the delay of the wrapper. Moreover, during testing, the test patterns are serially shifted-in and response is serially shifted-out. Thus, the test time increases significantly and at-speed testing is not possible.
(3) Memory built-in self-test (BIST): This method requires an additional inner circuit for on-chip test generation and response evaluation. This method is the costliest in terms of hardware overhead (additional chip area). The commercially available memory built-in self-test methods require about 3-4% area overhead for a 16K-bits memory. Also, due to additional circuit parasitic, about 1-2% performance penalty, such as signal propagation delays, occurs in memory read/write operations.
(4) Through ASIC functional test: For some small memory, ASIC vendors include simple write/read operations in the ASIC functional test. Most of the time, 1010 . . . 10 pattern is written and read. Generally, this method is applicable to only small memories and extensive testing is not done by this method.
Because the memory built-in self-test causes very little performance penalty at the chip's I/Os, only about 1-2% penalty in the memory read/write operations and provides an acceptable test time, the memory built-in self-test is increasingly used for embedded memories in system-on-chips. Various types of memory built-in self-test methods are available in the market. However, all the known memory built-in self-test methods are very costly in-terms of hardware overhead and allow only a limited number of memory test algorithms. Another limitation of these methods is that if fault diagnosis is desired, these methods require a significantly large amount of additional hardware to identify the failed bit locations.
As has been foregoing, the conventional test approach using the IC tester or design-for-test scheme is not cost-effective for testing embedded memories in a large scale integrated circuit such as an SoC IC.